library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;

-- This module performs a sign extension
entity sign_ext is
generic (N : integer := 32);
port(	input : in std_logic_vector (N/2-1 downto 0);
		output: out std_logic_vector (N-1 downto 0)
);
end sign_ext;

architecture Behavioral of sign_ext is
signal extend : std_logic_vector (N/2-1 downto 0);
begin

process (input)
begin

	if input(N/2-1) = '1' then
		for i in 0 to N/2-1 loop
			extend(i) <= '1';
		end loop;
	else
		for i in 0 to N/2-1 loop
			extend(i) <= '0';
		end loop;
	end if;
	
end process;

	output (N-1 downto N/2) <= extend;
	output (N/2-1 downto 0) <= input;

end Behavioral;

